Lars P. Tatum is a Postdoctoral Scholar working under the supervision of Prof. Tsu-Jae King Liu. He also received his Ph.D. from UC Berkeley in 2024 in Electrical Engineering & Computer Sciences where he was a National Science Foundation Graduate Research Fellow. Previously, he received a B.S. in Electrical Engineering from the University of Florida. He also held an internship position at Taiwan Semiconductor Manufacturing Company in 2023 developing emerging memory device technology. His research investigates novel semiconductor device approaches to enhance IC technology Power, Performance, Area, and Cost metrics.
Research
The future of IC technology faces significant challenges in maintaining improvements in Performance, Power, Area, and Cost (PPAC). Advancements in each of these aspects are increasingly interdependent, with improvements in one area often resulting in trade-offs in another. Lars’ research is focused on exploring novel approaches to advancing CMOS technology platforms that do not incur significant trade-offs in PPAC. To that end, he has worked to extend the functionality of transistor devices for compact circuit implementation, unconventional computing architecture, and low voltage operation. Lars has led the development of Negative Differential Resistance transistor technology (dubbed “NDRFET”), in which the device’s drain current decreases above a critical drain voltage. The NDRFET can enable the compact implementation of a variety of memory and logic circuits with > 2x the density of a traditional CMOS implementation. To date, the CMOS-compatible, Ferroelectric-based NDRFET is the only proposed approach which may achieve similar power/performance to mainstream CMOS technology with significantly reduced footprint area.
