Chirag received his B.Tech. degree from Indian Institute of Technology (IIT) Roorkee in 2021. After completing his undergraduate, he joined Micron Technology India as a DRAM memory design engineer where he worked on memory array circuits and high-speed IO interfaces for low-power DDR5 DRAM products. He is currently pursuing a Ph.D. in Prof. Sayeef Salahuddin’s group at University of California Berkeley. He works on energy-efficient hardware accelerators designed to tackle computationally hard optimization and machine learning algorithms. Through this work, he has developed expertise in digital and analog integrated circuit design, machine learning, as well as high-performance computing.
Research
The rapid increase in computing demand and energy consumption has pushed the need for specialized accelerators. This shift has led us to develop a series of hardware accelerators explicitly tailored to solve large-scale, NP-hard optimization problems while balancing performance with energy efficiency. These accelerator architectures follow Ising machine-like dynamics and consist of an in-memory computing engine, asynchronous neuron updates, and stochastic states sampler. Our implementations of such architectures on GPU, FPGA, and ASIC are capable of solving problems, such as the Max-CUT, traveling salesman, and other graph theory-related problems. Additionally, they enable sampling-based inference for machine learning and quantum lattice Hamiltonians. Particularly, the FPGA and ASIC-based accelerator demonstrates significant ~100x-10000x performance acceleration compared to heuristics implementations and annealing systems while being ~5x-100x more power efficient.
