Dasom Lee received a B.S. degree in material science from Sungkyunkwan University and an M.S. degree in material science from KAIST. After obtaining her M.S degree, she worked as a TCAD simulation engineer at SK hynix for several years. Currently, she is a third-year Ph.D. student in EECS working with professor Tsu-Jae King Liu at Berkeley. Her research interests focus on semiconductor devices for logic and memory applications. She explores innovative pathways to enhance the performance and characteristics of semiconductor devices through a combination of TCAD simulation, measurement, and experiment.
Research
As miniaturization of metal-oxide-semiconductor field-effect transistors (MOSFETs) continues, following Moore’s Law, the thickness of the semiconductor channel region must be scaled down proportionately with transistor gate length. To scale the transistor gate length below 10 nm, the semiconductor thickness must be scaled below 5 nm. In such ultra-thin-body MOSFETs, quantum confinement effects (changes in the semiconductor energy band structure) become significant, affecting charge-carrier field-effect mobility and transistor threshold voltage. Roughness of the interface between the gate-insulating layer and ultra-thin (“nanosheet”) semiconductor results in semiconductor thickness variations, degrading the effective carrier mobility. The Liu research group is investigating the use of “oxygen insertion technology” to smoothen the oxide-silicon interface and thereby mitigate this mobility degradation in ultra-thin-body MOSFETs, facilitating gate-length scaling to below 10 nm.
